In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like sync link dynamic tandem access memory (SLDRAMs) and rambus dynamic random access memory (RDRAMs). Double Data Rate (DDR, DDR2, DDR3), GDR (graphic), mobile DRAM or any device has DLL (for data output) and address setup and hold for both edges of the clock memory as well as other types of integrated circuits such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically have to be synchronized to external operations. For example, read data are placed on a data bus by the memory device in synchronism with an external clock signal. The memory device latches and drives the data onto the data bus at the proper times to successfully provide the read data. To latch the read data and drive it onto the data bus, an internal clock signal is developed in response to the external clock signal, and is typically applied to the data latches and data drivers contained in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock signal are synchronized to ensure the internal clock signal clocks the latches and data drivers at the proper times to successfully provide the read data. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” is used to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase shift is minimal, timing within the memory device can easily be synchronized to the external timing. To increase the rate at which commands can be applied and data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency may be well in excess of 500 MHz. It is contemplated that these frequencies will continue to increase. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches. Additionally, as the frequency of the external clock increases, variations in the duty cycle of the clock signal introduce a greater duty cycle error. In addition, time delay and phase shift are expected as signals propagate through internal circuitry. The variations of time delay and phase shift may be introduced by PVT (process-voltage-temperature) variations in extreme conditions. The clock signal is considered an analog input to the input buffer. At high frequencies and low VCC, the delay of the clock signal through the input buffer will vary and also the delay of the rising edge of clock versus the falling edge of clock will start to distort. When this happens, a single clock buffer will show duty cycle distortions on the output.
Low power applications also present clocking challenges. In many low power applications, lower frequency clocks may be used. Even though the clock runs at a lower frequency in these low power applications, the clock must operate at low voltages and low power. However, as the VCC associated with the low power components varies, it has been found that the duty cycle associated with the clocking signal may vary. In other words, with variations in VCC, the high time and low time of the clock signal may vary from the high time and low time of the external clock. As a result, duty cycle distortion may occur in the internal clock when compared to the external clock.
In some instances, a memory or other electronic component has a low pin count for outputs. Of course, memory holds data and a goal of storing memory is to maintain the integrity of the data. In order to get data out of a low pin count device more quickly, data from memory may be clocked out both on the rising clock edge and on the falling clock edge. In this type of application, the duty cycle is carefully maintained so that the data and commands are latched at an output and latched out of the memory and onto a data buffer at the correct time. If there is distortion in the duty cycle of the internal clock when compared to the external clock, the data placed onto the data bus may be incorrect, unreliable or lost. In any instance, the integrity of the data may be compromised.
Therefore, there is a need for a clock generator that functions in a variety of different types of circuits that reduces duty cycle distortion between an external clock and an internal clock.